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ST70235A
ASCOTTM DMT TRANSCEIVER
PRELIMINARY DATA
s DMT
MODEM FOR CPE ADSL, COMPATIBLE WITH THE FOLLOWING STANDARDS: - ANSI T1.413 ISSUE 2 - ITU-T G.992.1 (G.DMT) - ITU-T G.992.2 (G.LITE) 1 & 2) OR BITSTREAM INTERFACE
s SUPPORTS EITHER ATM (UTOPIA LEVEL s 16 BIT MULTIPLEXED MICROPROCESSOR
INTERFACE (LITTLE AND BIG ENDIAN COMPATIBILITY)
s ANALOG FRONT END MANAGEMENT s DUAL
LATENCY INTERLEAVED PATHS: FAST AND
s ATM'S PHY LAYER: CELL PROCESSING
(CELL DELINEATION, CELL INSERTION, HEC)
s ADSL'S OVERHEAD MANAGEMENT s REED SOLOMON ENCODE/DECODE s TRELLIS ENCODE/DECODE (VITERBI) s DMT MAPPING / DEMAPPING OVER 256
CARRIERS
GENERAL DESCRIPTION The ST70235A is the DMT modem and ATM framer of the STMicroelectronics ASCOTTM chipset. When coupled with ST70134 analog front-end and an external controller running dedicated firmware, the product fulfills ANSI T1.413 "Issue 2" DMT ADSL specification. The chip supports UTOPIA level 1 and UTOPIA level 2 interface. The ST70235A can be split up into two different sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections, with and without interleaving. The ST70235A is controlled and programmed by an external controller (ADSL Transceiver Controller, ATC) that sets the programmable coefficients. The firmware controls the initialization phase and carries out the consequent adaptation operations.
s FINE (2PPM) TIMING RECOVER USING
ROTOR AND ADAPTATIVE FREQUENCY DOMAIN EQUALIZING
s TIME DOMAIN EQUALIZATION s FRONT END DIGITAL FILTERS s 0.25m HCMOS7 TECHNOLOGY s 144 PIN TQFP s POWER CONSUMPTION: 0.4 WATT
APPLICATIONS Routers at SOHO, stand-alone modems, PC modems. TQFP144 Full Plastic (20 x 20 x 1.40 mm) ORDER CODE: ST70235A
October 2001
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ST70235A
Figure 1 : Block Diagram
TEST SIGNALS
CLOCK
TEST MODULE
DATA SYMBOL TIMING UNIT
VCXO
AFE INTERFACE
DSP FRONT-END
FFT/IFFT ROTOR
TRELLIS CODING MAPPER/ DEMAPPER
GENERIC TC REED/ SOLOMON
INTERFACE MODULE
UTOPIA
AFE CONTROL
AFE CONTROL INTERFACE
CONTROLLER INTERFACE
ATM SPECIFIC TC
CONTROLLER BUS
GENERAL PURPOSE I/Os
Transient Energy Capabilities ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of the device are to be able to withstand minimum 2000V for the HBM and minimum 250V for CDM. Latch-up The maximum sink or source current from any pin is limited to 200mA to prevent latch-up. ABSOLUTE MAXIMUM RATINGS
Symbol VDD 3.3 VDD 1.8 Ptot Tamb Rth J/A I3.3 I1.8 Parameter Supply Voltage Supply Voltage Total Power Dissipation Ambient Temperature 1m/s airflow Thermal Resistivity Current Consumption Current Consumption 0 38 14 135 Min. 3.0 1.62 Typ. 3.3 1.8 300 Max. 3.6 1.98 400 70 Unit V V mW C C/W mA mA
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ST70235A
Figure 2 : Pin Connection
DISABLE_COMP COMP_VDD_1.8 COMP_ROUT RESERVED RESERVED RESERVED CTRLDATA AFRXD_3 AFRXD_2 AFRXD_1 AFRXD_0 AFTXD_3 AFTXD_2 AFTXD_1 AFTXD_0 GP_OUT TESTSE
PDOWN
VDD 3.3
VDD 3.3
VDD 3.3
VDD 1.8
VDD 3.3
TRSTB
CLWD
MCLK
IDDq
TMS
TDO
VSS
VSS
VSS
VSS
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
VSS AD_0 AD_1 AD_2 VDD 3.3 AD_3 AD_4 VSS AD_5 AD_6 VDD 3.3 AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD 1.8 AD_12 VSS PCLK VDD 3.3 AD_13 AD_14 AD_15 VSS BE1 ALE VDD 3.3 CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VSS
TCK
TDI
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
VDD 1.8 RESERVED RESERVED RESERVED RESERVED RESERVED VSS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED VDD 3.3 RESERVED RESERVED RESERVED VSS RESERVED U_TX_ADDR_0 U_TX_ADDR_1 U_TX_ADDR_2 VDD 1.8 U_TX_ADDR_3 U_TX_ADDR_4 U_TX_DATA_0 U_TX_DATA_1 VDD 1.8 U_TX_DATA_2 U_TX_DATA_3 U_TX_DATA_4 U_TX_DATA_5 VDD 3.3 U_TX_DATA_6 U_TX_DATA_7 VSS
ST70235A
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VDD 1.8
VSS
VDD 3.3
VSS
VDD 3.3
GP_IN0
VSS
VDD 3.3
U_RXDATA_2
U_RXDATA_3
U_RXDATA_4
U_RXDATA_5
U_RXDATA_6
U_RXDATA_7
U_RX_ADDR_0
U_RX_ADDR_1
U_RX_ADDR_2
U_RX_ADDR_3
U_RX_ADDR_4
VDD 1.8
U_RXENBB
U_RXDATA_0
U_RXDATA_1
U_RXCLAV
U_RX_REFB
U_TX_REFB
U_TX_CLAV
U_TXENBB
U_RXSOC
U_TXSOC
U_RXCLK
U_TXCLK
VDD 3.3
GP_IN1
VSS
VSS
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ST70235A
PIN FUNCTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4/28 VSS AD_0 AD_1 AD_2 VDD 3.3 AD_3 AD_4 VSS AD_5 AD_6 VDD 3.3 AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD 1.8 AD_12 VSS PCLK VDD 3.3 AD_13 AD_14 AD_15 VSS BE1 ALE VDD 3.3 CSB WR_RDB RDYB OBC_TYPE INTB RESETB VSS VDD 3.3 U_RxData_0 U_RxData_1 VSS OZ OZ BD8STARP BD8STARP B B I I OZ I-PD O I TLCHT TLCHT BD4STARP TLCHTDQ BD4STARP TLCHT I I O I O I I I TLCHT TLCHT I C B B B BD8STARP BD8STARP BD8STARP B B B I TLCHT I B BD8STARP B B B BD8STARP BD8STARP B B B B B BD8STARP BD8STARP BD8STARP B B B B B BD8STARP BD8STARP B B B B BD8STARP BD8STARP B B B B B BD8STARP BD8STARP BD8STARP B B B Name Type PAD Type HCMOS7 BS 0V Ground Data 0 Data 1 Address / Data 2 (VSS + 3.3V) Power Supply Address / Data 3 Address / Data 4 0V Ground Address / Data 5 Address / Data 6 (VSS + 3.3V) Power Supply Address / Data 7 Address / Data 8 Address / Data 9 0V Ground Address / Data 10 Address / Data 11 (VSS + 1.8V) Power Supply Address / Data 12 0V Ground Processor clock (VSS + 3.3V) Power Supply Address / Data 13 Address / Data 14 Address / Data 15 0V Ground Address 1 Address Latch (VSS + 3.3V) Power Supply Chip Select Specifies the direction of the access cycle Controls the ATC bus cycle termination ATC Mode Selection (0 = i960; 1 = generic) Requests ATC interrupt service Hard reset 0V Ground (VSS + 3.3V) Power Supply Utopia RX Data 0 Utopia RX Data 1 0V Ground Function
ST70235A
PIN FUNCTIONS (continued)
Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name U_RxData_2 U_RxData_3 VDD 1.8 U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 VDD 3.3 U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 VSS U_RxADDR_4 GP_IN_0 VDD 3.3 GP_IN_1 VSS U_RxRefB U_TxRefB VDD 1.8 U_Rx_CLK U_Rx_SOC U_RxCLAV U_RxENBB VSS U_Tx_CLK U_Tx_SOC U_TxCLAV U_TxENBB VDD 3.3 VSS U_TxData_7 U_TxData_6 VDD 3.3 U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 I I I I TLCHT TLCHT TLCHT TLCHT I I I I I I TLCHT TLCHT I I I I OZ I TLCHT TLCHT BD8SCR TLCHT I OZ OZ I TLCHT BD8STARP BD8STARP TLCHT O I BD4STARP TLCHT O I I-PD TLCHTDQ I I I-PD TLCHT TLCHTDQ I I I I I I TLCHT TLCHT TLCHT TLCHT I I I I OZ OZ BD8STARP BD8STARP B B OZ OZ BD8STARP BD8STARP B B Type OZ OZ PAD Type HCMOS7 BD8STARP BD8STARP BS B B Utopia RX Data 2 Utopia RX Data 3 (VSS + 1.8V) Power Supply Utopia RX Data 4 Utopia RX Data 5 0V Ground Utopia RX Data 6 Utopia RX Data 7 (VSS + 3.3V) Power Supply Utopia RX Address 0 Utopia RX Address 1 Utopia RX Address 2 Utopia RX Address 3 0V Ground Utopia RX Address 4 General purpose input 0 (VSS + 3.3V) Power Supply General purpose input 1 0V Ground 8kHz clock to ATM device 8kHz clock from ATM device (VSS + 1.8V) Power Supply Utopia RX Clock Utopia RX Start of Cell Utopia RX Cell Available Utopia RX Enable 0V Ground Utopia TX Clock Utopia TX Start of Cell Utopia TX Cell Available Utopia TX Enable (VSS + 3.3V) Power Supply 0V Ground Utopia TX Data 7 Utopia TX Data 6 (VSS + 3.3V) Power Supply Utopia TX Data 5 Utopia TX Data 4 Utopia TX Data 3 Utopia TX Data 2 5/28 Function
ST70235A
PIN FUNCTIONS (continued)
Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 6/28 Name VDD 1.8 U_TxData_1 U_TxData_0 U_TxADDR_4 U_TxADDR_3 VDD 1.8 U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 RESERVED VSS RESERVED RESERVED RESERVED VDD 3.3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED VSS RESERVED RESERVED RESERVED RESERVED RESERVED VDD 1.8 VSS RESERVED RESERVED TDI TDO TMS VDD 3.3 TCK VSS TRSTB TESTSE GP_OUT I-PD I O TLCHTDQ TLCHTDQ BD8STARP none O I-PD TLCHTDQ I-PU OZ I-PU BD4STARP BD4STARP TLCHTUQ BD4STARP TLCHTUQ TLCHTDQ TLCHTDQ TLCHTDQ TLCHTDQ BD4STARP BD4STARP BD4STARP BD4STARP BD4STARP BD4STARP BD4STARP BD4STARP BD4STARP BD4STARP I I I TLCHT TLCHT TLCHT BD4STARP I I I I I I I TLCHT TLCHT TLCHT TLCHT I I I I Type PAD Type HCMOS7 BS Function (VSS + 1.8V) Power Supply Utopia TX Data 1 Utopia TX Data 0 Utopia TX Address 4 Utopia TX Address 3 (VSS + 1.8V) Power Supply Utopia TX Address 2 Utopia TX Address 1 Utopia TX Address 0 Reserved 0 0V Ground Reserved 1 Reserved 2 Reserved 3 (VSS + 3.3V) Power Supply Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 0V Ground Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 (VSS + 1.8V) Power Supply 0V Ground Reserved 15 Reserved 16 JTAG I/P JTAG O/P JTAG Made Select (VSS + 3.3V) Power Supply JTAG Clock 0V Ground JTAG Reset Enables scan test mode General purpose output
ST70235A
PIN FUNCTIONS (continued)
Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name PDOWN VDD 3.3 AFRXD_0 AFRXD_1 AFRXD_2 AFRXD_3 VSS CLWD MCLK CTRLDATA VDD 3.3 COMP_VDD_1.8 COMP_ROUT VSS DISABLE_COMP RESERVED VDD 1.8 IDDq AFTXD_0 AFTXD_1 VSS AFTXD_2 AFTXD_3 VDD 3.3 O O BD8STARP BD8STARP O O I O O TLCHT BD8STARP BD8STARP none O O I O COMP_1V60 COMP_1V60 COMP_1V60 TLCHTDQ none I I O TLCHT TLCHT BD4STARP I C O I I I I TLCHT TLCHT TLCHT TLCHT I I I I Type O PAD Type HCMOS7 BD4STARP BS O Function Power down analog front end (Reset) (VSS + 3.3V) Power Supply Receive data nibble Receive data nibble Receive data nibble Receive data nibble 0V Ground Start of word indication Master clock Serial data Transmit channel (VSS + 3.3V) Power Supply Compensation Cell VDD 1.8V (see note 1) Compensation Cell Resistor (see note 1) 0V Ground Disable Compensation Cell (see note 1) Reserved (VSS + 1.8V) Power Supply Test pin, active high Transmit data nibble Transmit data nibble 0V Ground Transmit data nibble Transmit data nibble (VSS + 3.3V) Power Supply
Note: Compensation cell - The COMP_OUT pin must be connected at GND by a 100K resistor on board. Specifications of the resistor have to meet the following requirements: 5% allowed on the value, 1% is preferred. Advice is given to place the resistor so that there will be the shortest path between it and the pin. Using the DISABLE_COMP signal is possible to disable the slew rate control of IOs, in this mode the IOs are however still functional, but dynamic performances are affected. An internal pull-down on DISABLE_COMP pin enables the slew rate control of IOs, an external pull-up resistor (connected at 3.3V) must be inserted in order to disable the slew rate control.
Table 1 : I/O Driver Function
Driver BD4STARP BD8STARP TLCHTDQ TLCHTUQ TLCHT Function TTL Three Volt capable Schmitt Trigger Bidirectional Pad Buffer, 4mA, with Test pins, with Active Slew Rate Control TTL Three Volt capable Schmitt Trigger Bidirectional Pad Buffer, 8mA, with Test pins, with Active Slew Rate Control TTL Three Volt capable Input Buffer with Active Pull-Down and Test pin TTL Three Volt capable Input Buffer with Active Pull-Up and Test pin TLL Three Volt capable Input Pad Buffer 7/28
ST70235A
PIN SUMMARY
Mnemonic Power Supply VDD 3.3 VDD 1.8 VSS ATC INTERFACE ALE PCLK CSB BE1 WR_RDB RDYB INTB AD OBC_TYPE TDI TDO TCK TMS TRSTB AFRXD AFTXD CLWD PDOWN CTRLDATA MCLK U_RxData U_TxData U_RxADDR U_TxADDR U_RxCLAV U_TxCLAV U_RxENBB U_TxENBB U_RxSOC U_TxSOC U_RxCLK U_TxCLK U_RxRefB U_TxRefB 8/28 I I I I I OZ O IO I-PD I-PU OZ I-PD I-PU I-PD I O I O O I OZ I I I OZ OZ I-TTL I-TTL OZ I-TTL I-TTL I-TTL O I-TTL I O I O O C B I I I O O I I O I C C O I C I I I I O O B I 1 1 1 1 1 1 1 16 1 1 1 1 1 1 4 4 1 1 1 1 8 8 5 5 1 1 1 1 1 1 1 1 1 1 Receive data nibble Transmit data nibble Start of word indication Power down analog front end Serial data transmit channel Master cloc Receive interface Data Transmit interface Data Receive interface Address Transmit interface Address Receive interface Cell Available Transmit interface Cell Available Receive interface Enable Transmit interface Enable Receive interface Start of Cell Transmit interface Start of Cell Receive interface Utopia Clock Transmit interface Utopia Clock 8kHz reference clock to ATM device 8kHz reference clock from ATM device Used to latch the address of the internal register to be accessed Processor clock Chip selected to respond to bus cycle Address 1 (not multiplexed) Specifies the direction of the access cycle Controls the ATC bus cycle termination Requests ATC interrupt service Multiplexed Address/Data bus Select between i960 (0) or generic (1) controller interface Refer to section (VSS + 3.3V) Power supply (VSS + 1.8V) Power supply 0V Ground Type Number BS Type of Signals Function
TEST ACCESS PART INTERFACE
ANALOG FRONT END INTERFACE
ATM UTOPIA INTERFACE
ST70235A
PIN SUMMARY (continued)
Mnemonic MISCELLANEOUS GP_IN GP_OUT RESETB TESTSE IDDq COMP_ROUT DISABLE_COMP I-PD O I I I O I-PD I O I none none none I 2 1 I none none 1 1 General purpose input General purpose output Hard reset Enable scan test mode Test pin, active high Compensation cell resistor Disable compensation cell Type BS Type Number of Signals Function
= Input, CMOS levels = Input with pull-up resistance, TTL levels I-PD = Input with pull-down resistance, TTL levels I-TTL = Input TTL levels O = Push-pull output OZ = Push-pull output with high-impedance state IO = Input / Tristate Push-pull output BS cell = Boundary-Scan cell I = Input cell O = Output cell B = Bidirectional cell C = Clock Main Block Description The following drawings describe the sequence of functions performed by the chip. DSP Front-End The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equalizer. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End lnterface transfers 16-bit words, multiplexed on 4 input/output signals. Word transfer is carried out in 4 clock cycles. The Decimator receives 16-bit samples at 8.8MHz (as sent by the Analog Front-End chip: ST70134) and reduces this rate to 2.2MHz. The Time Equalizer (TEQ) module is a FIR filter with programmable coefficients. Its main purpose
I I-PU
is to reduce the effect of Inter-Symbol Interferences (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering, clipping, delay equalization and interpolation. The sidelobe filtering and delay equalization are implemented by IIR Filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2MHz and generates samples at a rate of 8.8MHz. DMT Modem This module is a programmable DSP unit. Its instruction set enables the basic functions of the DMT algorithm like FFT, IFFT, Scaling, Rotor and Frequency Equalization (FEQ) in compliance with ANSI T1.413 specifications. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages. In other words, the Fast Fourier Transform process is used to transform from time domain to frequency domain (receive path). 1024 time samples are processed. After the first stage time domain equalization and FFT block an ICI (InterCarrier Interference) free information stream turns out.
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ST70235A
Figure 3 : DSP Front-End Receive
BYPASS
From Analog Front-end
IN SELECT
AFE I/F
DEC
TEC
To DMT Modem
Figure 4 : DSP Front-End Transmit
From DMT Modem
FILTERING CLIPPING DELAY EQUALIZER
INTERPOLATOR
AFE I/F
OUT SELECT
To Analog Front End
Figure 5 : DMT Modem (Rx & Tx)
TREILLIS CODING DECODING
To/From DSP FE
FFT IFFT
FEQ FTG
ROTOR
MAPPER DEMAPPER
To/From TC
FEQ COEFFICIENTS
MONITOR
FEQ Update
Monitor Indications
This stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. To compensate, a Frequency domain equalizer (FEQ) and a Rotor (phase shifter) are implemented. The frequency domain equalization performs an operation on the received vector in order to match it with the associated point in the constellation. The coefficient used to perform the equalization are floating point, and may be updated by hardware or software, using a mechanism of active and inactive table to avoid DMT synchro problems.In the transmit path, the
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IFFT reverses the DMT symbol from frequency domain to time domain. The IFFT block is preceded by Fine Tune Gain (FTG) and Rotor stages, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The Inverse Fast Fourier Transform process is used to transform from frequency domain to time domain (transmit path). 256 positive frequencies are processed, giving 512 samples in the time domain.
ST70235A
The FFT module is a slave DSP engine controlled by the firmware running on an external controller. It works off line and communicates with other blocks through buffers controlled by the "Data Symbol Timing Unit". The DSP executes a program stored in a RAM area, which constitutes a flexible element that allows for future system enhancements. DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the ends (transmitter and receiver) do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. Eventually that leads to achieve less than 2ppm between the two ends. Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This means to identify a point in a 2D QAM constellation plane. The Demapper supports Trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the Trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the mapper receives a bit stream from the Trellis encoder and modulates the bit stream on a set of carriers (up to 256). It generates coordinates for 2n QAM constellation, where n < 15 for all carriers. The Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. This feature can be disabled.The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T 1.4 13. Additions described in the Issue 2 of this specification are also supported. The data received from the demapper may be split into two paths, one dedicated to an interleaved data flow the other one for a fast data flow. No external RAM is needed for the interleaved path. The interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. After deinterleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the error bytes and have labelled them with an "erasure indication". Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer.After the RS decoder, the corrected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support Physical layer related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). The deframer also performs a CRC check (Cyclic Redundancy Check) on the received frame and generates events in case of error detection.Event counters can be read by management processes. The outputs of the deframer are an interleaved and a fast data streams. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module.
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ST70235A
Figure 6 : Generic TC Layer Functions
Indication Bits AOC EOC
To/From Demapper
FAST DATA PATX MERGER RS CODING DECODING
F
PMD SCRAMBLER DESCRAMBLER PMD SCRAMBLER DESCRAMBLER
F FRAMER DEFRAMER I To ATM TC
INTERLEAVER DE-INTERLEAVER
I
ATM Specific TC Layer Functions The 2 bytes streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER Figure 7 : ATM Specific TC Layer Functions
measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. The interface module collects cells (from the cell-based function module). Cells are stored in FIFO's (424 bytes or 8 cell wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one providing a Utopia level 1 interface and the other a Utopia level 2 interface.
BER
From Generic TC
FAST
CELL SCRAMBLER DESCRAMBLER SYNCHRONIZER
HEC
CELL INSERTION/ FILTER
To Interface Module
SLOW
CELL SCRAMBLER DESCRAMBLER SYNCHRONIZER
HEC
CELL INSERTION/ FILTER
BER
Figure 8 : Interface Module
UTOPIA FAST ATM
LEVEL 1
UTOPIA From ATM TC SLOW ATM
LEVEL 2
UTOPIA
LEVEL 1
UTOPIA
LEVEL 2
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ST70235A
DMT Symbol Timing Unit (DSTU) The DSTU interfaces with various modules, like DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS, Monitor and Transceiver Controller. It consists of a real time and a scheduler modules. The real time unit generates a timebase for the DMT symbols (sample counter), superframes (symbol counter) and hyper-frames (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. ST70235A interfaces Data and addresses are multiplexed ST70235A works in 16 bits data access, so address bit 0 is not used. Address bit 1 is not multiplexed with data. It has its own pin : BE1. Byte access are not supported. Access cycle read or write are always in 16 bits data wide, ie bit address A0 is always zero value. The interrupt request pin to the processor is INTB, and is an Open Drain output. The ST70235A supports both little and big endian. The default feature is big endian. Figure 9 : ST70235A Interfaces
AFE INTERFACE TO ADSL LINE (ST70134) RESET JTAG CLOCK ST70235A
PROCESSOR INTERFACE (ATC)
Overview
See Figure 9.
DIGITAL INTERFACE UTOPIA
Generic Interface This interface is suitable for a number of processors using a multiplexed Address/data bus. In this case, synchronization of the input signals with PCLK pin is not necessary.
Processor Interface (ATC)
The ST70235A is controlled and configured by an external processor across the processor interface. All programmable coefficients and parameters are loaded through this path.
Figure 10 : Generic Processor Interface Write Timing Cycle
MClk ALE Talew Tale2cs CSB Tavs Tavh Trdy2cs
Address/DATA Twr2Mclk Twr2d WRB RDYB Twr2rdy 1: RDB = WR_RDB is high. Tcsre Tmclk Trdy2wr
1
Tcs2wr
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ST70235A
Figure 11 : Generic Processor Interface Read Timing Cycle
MClk Tale2Z ALE Talew Tale2cs CSB Tavh Tavs Address/DATA T rd2Mclk T cs2rd Twrw RDYB T rd2rdy 1: WRB = BE1 is high. T csre Tmclk T rdy2rd Tdvs T dvh T rdy2cs
RDB
1
Generic processor interface Cycle Timing
All AC characteristics are indicated for a 100pF capacitive load.Cycle timing for generic interface. Table 2 : Cycle timing
Symbol Tcsre Talew Tavs Tavh Tale2cs Tale2Z Tcs2wr Tcs2rd Twr2d Twr2rdy Trd2rdy Trdy2wr Trdy2rd Tdvs Tdvh Trdy2cs Tmclk Twr2Mclk Trd2Mclk Access Time Ale pulse width Address valid setup time Address valid hold time ALE to CSB ALE to high Z state of bus CSB to WRB CSB to RDB WR to data WR to Dy asserted RD to Rdy asserted Rdyb to WRB Rdyb to RDB Data valid setup time Data valid hold time RdyB to CSB master clock timing : cf specifications Setup time according to the master clock Setup time according to the master clock 10 10 ns ns 0 0 10 1/2 Tmclk 0 Tmclk 0 0 15 60 60 12 10 10 0 50 Parameters Minimum Maximum 900 Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
The timing are generally presented with the write signal, but as shown on the read diagram, they are also valid for the read signal, so for example the Trdy2wr timing is the same as what can be Trdy2rd.
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ST70235A
Generic Processor Interface Pins and Functional Description
Name AD[0..15] ALE RDB WRB CSB RDYB INTB Type I/O I I I I OZ O Function Multiplexed address / data bus Address Latch Enable Read cycle indication Write cycle indication Chip Select Bus cycle ready indication Interrupt
PHY RECEIVE
Figure 12 : Receive Interface
PHY RxREF* RxCLAV RxENB* RxCLK RxDATA RxSOC 8 CELL RECEIVE ATM
Digital interface ATM or serial
Digital Interface before modulation demodulation. for and data to from the the loop loop after
Figure 13 : Transmit Interface
PHY TxREF* TxCLAV ATM LAYER
This interface collects cells (from the cell based function module) or a byte stream (from the deframer). Cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. 2 kinds of interface are allowed: - Utopia Level 1 - Utopia Level 2 The interface selection is programmed by writing the Utopia PHY address register. Only one interface can be enabled in a ST70235A configuration. Utopia Level 1 supports only one PHY device. Utopia Level 2 supports multi-PHY devices (See Utopia Level 2 specifications). Each buffer provides storage for 8 ATM cells (both directions for Fast and Interleaved channel). The Utopia Level 2 supports point to multipoint configurations by introducing an addressing capability and by making distinction between polling and selecting a device.
TxENB* PHY TRANSMIT TxCLK TxDATA TxSOC 8 CELL TRANSMIT
Utopia Level 1 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM is the Receive direction. Figures 12 & 13 show the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The Utopia interface transfers one byte in a single clock cycle, as a result cells are transformed in 53 clock cycles. Both transmit and receive are synchronized on clocks generated by the ATM layer chip, and no specific relationship between receive and transmit clocks is required. In this mode, the ST70235A can only support one data flow : either interleaved or fast.
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ST70235A
Figure 14 : Timing (Utopia 2 Receive Interface)
Detection Polling Polling: Selection Polling
1 RxClk RxAddr RxClav
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1F N-3
1F
N+1
1F
N-1
1F
N
1F
N+3
1F
N-1
1F
N-3
1F N-3
N-3
1F N-3
N+1
1F N+1
N+2
N-3
N+1
N-1
N
N+3
N-1
RxEnb* RxData P41 P42 RxSOC Cell transmission from: PHY N PHY N-3 P43 P44 P45 P46 P47 P48 XX H1 H2 H3
Pin Description
Name RxClav RxEnb 1 Type O I Meaning Receive Cell available Receive Enable Usage Signals to the ATM chip that the ST70235A has a cell ready for transfer Signals to the ST70235A that the ATM chip will sample and accept data during next clock cycle Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from ST70235A chip to ATM chip, byte wide. Rx Data [7] is the MSB. Identifies the cell boundary on RxData Indicate to the ATM layer chip that RxData contains the first valid byte of a cell Active low signal Remark Remains active for the entire cell transfer RxData and RxSOC could be tri-state when RxEnb* is inactive (high). Active low signal
RxClk RxData RxSOC
I O O
Receive Byte Clock Receive Data (8bits) Receive Start Cell
RxRef 1
Note
O
Reference Clock
8 kHz clock transported over the network
1. Active low signal
When RxEnb is asserted, the ST70235A reads data from its internal fifo and presents it on RxData and RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on the rising edge of RxSOC on the rising edge of RxClk.
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ST70235A
Pin Description
Name TxClav TxEnb 1 TxClk TxData TxSOC TxRef 1
Note
Type O I I I I I
Meaning Transmit Cell available Transmit Enable Transmit Byte Clock Transmit Data (8bits) Transmit Start of Cell Reference Clock
Usage
Remark
Signals to the ATM chip that the physical Remains active for the entire layer chip is ready to accept a complete cell cell transfer Signals to the ST70235A that TxData and TxSOC are valid Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from ATM layer chip to ST70235A, byte wide. TxData [7] is the MSB. Identifies the cell boundary on TxData 8kHz clock from the ATM layer chip TxData contains the first valid byte of the cell.
1. Active low signal
The ST70235A samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC Electrical Characteristics
Symbol F Tc Tj Trf L Clock frequency Clock duty cycle Clock peak to peak jitter Clock rise fall time Load Parameters Minimum 1.5 40 Maximum 25 60 5 4 100 Unit MHz % % ns pF
TxData, TxSOC, TxAddr, TxEnb, AC Electrical Characteristics
Symbol T5 T6 L Parameters Input set-up time to TxClk Hold time to TxClk Load Minimum 10 1 100 Maximum Unit ns ns pF
Note: Tx data hold time is 1.2ns. All the UTOPIA hold time are guarantee by design. RxData, RxSOC, RxClav, TxClav, AC Electrical Characteristics
Symbol T7 T8 T9 T10 T11 T12 L Parameters Input set-up time to TxClk Hold time to Tx Clk Signal going low impedance to RxClk Signal going High impedance to RxClk Signal going low impedance to RxClk Signal going High impedance to RxClk Load Minimum 10 1 10 0 1 1 100 Maximum Unit ns ns ns ns ns ns pF 17/28
ST70235A
RxAddr, RxEnb, AC Electrical Characteristics
Symbol T5 T6 L Parameters Input setup time to RxClk Hold time to RxClk Load Minimum 10 1 100 Maximum Unit ns ns pF
Figure 15 : Timing (Utopia 2 Transmit Interface)
Detection Polling Polling: Selection Polling
1 TxClk TxAddr TxClav
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1F N+1
1F
N
1F
N+3
1F
N+2
1F
N-1
1F
N
1F
N+3
1F N+3
N+3
1F N+3
N-2
1F
N-3
N+1
N
N+3
N+2
N-1
N
N+1
N-2
TxEnb* TxData TxSOC Cell transmission from: PHY N PHY N+3 P45 P46 P47 P48 H1 H2 H3 H4
Figure 16 : Timing Specification (Utopia 2)
Clock T5, T7 Signal (at input) Signal (highz) T11 T9 T12 T10 T6, T8
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ST70235A
DIGITAL INTERFACE Utopia Level 2 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM is the Receive direction. Figure 17 shows the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles.Both transmit and receive interfaces are synchronized on clocks generated by the ATM layer chip, and no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level 2 supports point to multipoint configurations by introducing on addressing capability and by making a distinction between polling and selecting a device: - The ATM chip polls a specific physical layer chip by putting its address on the address bus when the Enb* line is asserted. The addressed physical layer answers the next cycle via the Clav line reflecting its status at that time. - The ATM chip selects a specific physical layer by putting its address on the address bus when the Enb* line is deasserted and asserting the Enb* line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer (see Figure 17). Utopia Level 2 Signals The physical chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the fifo of the physical layer chip. The cell exchange proceeds like: a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b) The ATM chips selects a physical layer chip, then starts the transfer by asserting RxEnb*. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled RxEnb* active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. Figure 17 : Signal at Utopia Level 2 Interface
PHY ATM
RxADDR 5 RxCLAV 1 RxENB* PHY RECEIVE RxCLK RxDATA 8 ATM RECEIVE
RxSOC RxREF*
TxADDR 5 TxCLAV 1 TxENB* PHY TRANSMIT TxCLK TxDATA 8 ATM TRANSMIT
TxSOC TxREF*
ST70235A Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The ST70235A supports only the required mode, this mode is referred to as "Operation with 1 TxClav and 1 RxClav". PHY Device Identification The ST70235A holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields in the Utopia PHY address register.
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ST70235A
Beware that an incorrect address configuration may lead to bus conflicts. A feature is defined to disable (tri-state) all outputs of the Utopia interface. It is enabled by the TRI_STATE_EN bit in the Rx_interface control register. Pin Description Utopia 2 (Receive Interface)
Name RxClav Type O Meaning Receive Cell available Usage Signals to the ATM chip that the STLC60135 has a cell ready for transfer Signals to the physical layer that the ATM chip will sample and accept data during next clock cycle Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, from physical layer chip to ATM chip, byte wide. Identifies the cell boundary on RxData Use to select the port that will be active or polled 8kHz clock transported over the network Indicate to the ATM layer chip that RxData contains the first valid byte of a cell. Remark Remains active for the entire cell transfer RxData and RxSOC could be tri-state when RxEnb* is inactive (high)
RxEnb*
I
Receive Enable
RxClk
I
Receive Byte Clock
RxData
O
Receive Data (8 bits)
RxSOC
O
Receive Start Cell
RxAddr RxRef *
I O
Receive Address (5 bits) Reference Clock
Note
*Active low signal
Pin Description Utopia 2 (Transmit interface)
Name TxClav Type O Meaning Transmit Cell available Usage Signals to the ATM chip that the physical layer chip is ready to accept a cell Signals to the physical layer that TxData and TxSOC are valid Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data, to physical layer chip to ATM chip, byte wide. Identifies the cell boundary on TxData Use to select the port that will be active or polled 8kHz clock from the ATM layer chip Remark Remains active for the entire cell transfer
TxEnb*
I
Transmit Enable
TxClk
I
Transmit Byte Clock
TxData TxSOC TxAddr TxRef *
I I I I
Transmit Data (8 bits) Transmit Start of Cell Transmit Address (5 bits) Reference Clock
Note
*Active low signal
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ST70235A
Analog Front End Control Interface The Analog Front End Interface is designed to be connected to the ST70134 Analog Front End component. Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to table 1 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 18. Figure 18 : Transmit Word Timing Diagram
MCLK
The ST70235A fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 2 for the bit / pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD must repeat after 4 MCLK cycles.
CLWD
AFTXD Cycle0 GP_OUT Test0 Test1 Test2 Test3 Cycle1 Cycle2 Cycle3
Figure 19 : Receive Word Timing Diagram
MCLK
CLWD
AFRXD Cycle0 GP_IN(0) Test0 Test1 Test2 Test3 Cycle1 Cycle2 Cycle3
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ST70235A
Figure 20 : Transmit Interface Table 3 : Transmitted Bits Assigned to Signal / Time Slot
Cycle 0
Tv AFTXD
MCLK
Cycle 1 b4 b5 b6 b7
Cycle 2 b8 b9 b10 b11
Cycle 3 b12 b13 b14 b15
AFTXD[0] AFTXD[1] AFTXD[2]
b0 b1 b2 b3
Figure 21 : Receive Interface
MCLK Ts Th AFRXD Tc CLWD
AFTXD[3]
Table 4 : Transmitted Bits Assigned to Signal / Time Slot
Cycle 0 AFRXD[0] AFRXD[1] AFRXD[2] AFRXD[3] b0 b1 b2 b3 Cycle 1 b4 b5 b6 b7 Cycle 2 b8 b9 b10 b11 Cycle 3 b12 b13 b14 b15
Table 5 : Master Clock (MCLK) AC Electrical Characteristics
Symbol F Tper Th Parameter Clock Frequency Clock Period Clock Duty Cycle 40 Minimum Typical 35.328 28.3 60 Maximum Unit MHz ns %
Table 6 : AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol Tv Tc Parameter Data Valid Time Data Valid Time Minimum 0 0 Typical Maximum 13 10 Unit ns ns
Table 7 : AFRXD AC Electrical Characteristics
Symbol Ts Th Parameter Data setup Time Data hold Time Minimum 5 5 Typical Maximum Unit ns ns
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ST70235A
Tests, Clock, JTAG Interface - Mclk: Master Clock (35.328MHz) generated by VCXO - ATM receive interface, asynchronous clock generated by Utopia Master - ATM transmit interface, asynchronous clock generated by Utopia Master - ATC clock (Pclk): external asynchronous clock (synchronous with ATC in case of i960 specific interface) JTAG TP interface: Standard Test Access Port, Used with the boundary scan for chip and board testing. This JTAG TAP interface consists in 5 signals: TDI, TDO, TCK & TMS. TSRTB: Test Reset, reset the TAP controller. TRSTB is an active low signal. Table 8 : Boundary Scan Chain Sequence
Signal Name Ad[0] Ad[1] Ad[2] Ad[3] Ad[4] Ad[5] Ad[6] Ad[7] Ad[8] Ad[9] Ad[10] Ad[11] Ad[12] Pclk Ad[13] Ad[14] Ad[15] Be1 Ale Sequence Number IO2 IO3 IO4 IO6 IO7 IO9 IO10 IO12 IO13 IO14 IO16 IO17 IO19 IO21 IO23 IO24 IO25 IO27 IO28 BS Type B B B B B B B B B B B B B C B B B I C
Table 8 : Boundary Scan Chain Sequence
Signal Name Csb Wr_Rdb Rdyb Obc_Type Intb Resetb U_Rxdata[0] U_Rxdata[1] U_Rxdata[2] U_Rxdata[3] U_Rxdata[4] U_Rxdata[5] U_Rxdata[6] U_Rxdata[7] U_Rxaddr[0] U_Rxaddr[1] U_Rxaddr[2] U_Rxaddr[3] U_Rxaddr[4] Gp_In[0] Gp_In[1] U_Rxrefb U_Txrefb U_Rxclk U_Rxsoc U_Rxclav U_Rxenb U_Txclk U_Txsoc U_Txclav U_Txenb U_Txdata[7] U_Txdata[6] Sequence Number IO30 IO31 IO32 IO33 IO34 IO35 IO38 IO39 IO41 IO42 IO44 IO45 IO47 IO48 IO50 IO51 IO52 IO53 IO55 IO56 IO58 IO60 IO61 IO63 IO64 IO65 IO66 IO68 IO69 IO70 IO71 IO74 IO75 BS Type I I B I O I B B B B B B B B I I I I I I I O I C I O I C I O I I I
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ST70235A
Table 8 : Boundary Scan Chain Sequence
Signal Name U_Txdata[5] U_Txdata[4] U_Txdata[3] U_Txdata[2] U_Txdata[1] U_Txdata[0] U_Txaddr[4] U_Txaddr[3] U_Txaddr[2] U_Txaddr[1] U_Txaddr[0] Reserved 0 Reserved 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 TDI TDO TMS TCK TRSTB Testse GP_Out Sequence Number IO77 IO78 IO79 IO80 IO82 IO83 IO84 IO85 IO87 IO88 IO89 IO90 IO92 IO93 IO94 IO96 IO97 IO98 IO99 IO100 IO101 IO103 IO104 IO105 IO106 IO107 IO110 IO111 IO112 IO113 IO114 IO116 IO118 IO119 IO120 BS Type I I I I I I I I I I I O O O O O O O O NONE O I I I I O O O NONE NONE NONE NONE NONE C O Bits from 3 to 15 are reserved GP_OUT RW [2] 1 Field GP_IN Type R Position Bits [0,1] Length 2 Function Sampled level on pins GP_IN Output level on pins GP_OUT
Table 8 : Boundary Scan Chain Sequence
Signal Name Pdown Afrxd[0] Afrxd[1] Afrxd[2] Afrxd[3] Clwd Mclk Ctrldata Disable_Comp Iddq AFTXD[0] AFTXD[1] AFTXD[2] AFTXD[3] Sequence Number IO121 IO123 IO124 IO125 IO126 IO128 IO129 IO130 IO135 IO138 IO139 IO140 IO142 IO143 BS Type O I I I I I C O I C NONE NONE NONE NONE
General purpose I/O register (0x40)
Reset Initialization The ST70235A supports two reset modes: - A 'hardware' reset is activated by the RESETB pin (active low). A hard reset occurs when a low input value is detected at the RESETB input. The low level must be applied for at least 1ms to guarantee a correct reset operation. All clocks and power supplies must be stable for 200ns prior to the rising edge of the RESETB signal. - 'Soft' reset activated by the controller write access to a soft reset configuration bit. The reset process takes less than 10000 MCLK clock cycles.
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ST70235A
ELECTRICAL SPECIFICATIONS Generic DC Electrical Characteristics The values presented in the following table apply for all inputs and/or outputs unless otherwise specified. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device. IO Buffers Generic DC Characteristics
Symbol IIN IOZ IPU IPD RPU RPD Parameter Input Leakage Current Tristate Leakage Current Pull up Current Pull Down Current Pull up Resistance Pull Down Resistance Test Condition VIN = VSS, VDD no pull up /pull down VIN = VSS, VDD no pull up /pull down VIN = VSS VIN = VDD VIN = VSS VIN = VDD Minimum -4 -4 -15 15 -66 66 50 50 Typical Maximum 4 4 -125 125 Unit A A A A K K
Input/ Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless otherwise specified.
Symbol VIL VIH VHY VOL VOH Parameter Low Level Input Voltage High Level Input Voltage Schmitt Trigger Hysteresis Low Level Output Voltage High Level Output Voltage Slow edge < 1V/s IOUT = XmA* IOUT = XmA* 2.4 2.0 0.4 0.7 0.4 Test Condition Minimum Typical Maximum 0.8 Unit V V V V V
* The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 4 and 8mA.
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ST70235A
TQFP144 PACKAGE MECHANICAL DATA Figure 22 : Package Outline TQFP144
A A2 144 e A1 109 0,076 mm 0.03 inch SEATING PLANE
1
108
36
73
c
37
D3 D1 D
72
L1
L
E3 E1 E
K
0,25 mm .010 inch GAGE PLANE
Millimeter Dimension Minimum A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 22.00 20.00 17.50 0.50 22.00 20.00 17.50 0.60 1.00 0 (minimum), 7 (maximum) 0.75 0.018 1.40 0.22 Typical Maximum 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.0067 0.0035 Minimum
Typical
B
Inch Maximum 0.063 0.006 0.055 0.0087 0.057 0.011 0.008 0.866 0.787 0.689 0.020 0.866 0.787 0.689 0.024 0.039 0.030
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ST70235A
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ST70235A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - All Rights Reserved
ST70235A.REF
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